1. Field of the Invention
The present invention relates to planarizing a workpiece and, more particularly, to planarizing a workpiece employed in fabricating semiconductor chips.
2. Description of the Prior Art
During the process of fabricating semiconductor chips (integrated circuits), metal conductors are used to interconnect the many microelectronic components which are disposed on a workpiece--for example, a substrate of a semiconductor material such as silicon. Typically, a thin, substantially flat, usually circular wafer of the semiconductor material is processed to include multiple thin layers of metal conductors, insulators and metal liners, in addition to the microelectronic components such as complementary metal oxide semiconductors (CMOS) devices.
FIG. 1A shows a typical semiconductor wafer W during an interim step in a conventional fabrication process. The wafer W has two major sides 10 and a plurality of minor sides 12. As shown in FIG. 1B, the minor sides 12 form, for example, a substantially continuous circular side S around the wafer W. The wafer includes, for example, a Si substrate 14 having an insulator 16 (eg, a SiO.sub.2 layer), a conductor 18 (eg, a Cu layer) and a microelectronic component 20 (eg, a CMOS device) disposed thereon. The component 20 is disposed, for example, in the substrate 14 and/or in the insulator 16 The conductor layer 18 forms substantially all of one major side 10 and forms part of the minor sides 120. The layer 18 is, eg, Cu, Al, Ti, Ta, Fe, Ag, Au, alloys or even magnetic films.
As wiring densities in semiconductor chips increase, multiple levels of the conductor layers 18 are required to achieve interconnections of the components 20. Thus, planarization of each conductor layer 18 and each insulator or dielectric layer 16 is a critical step in the chip fabrication process.
Various planarization methods and apparatus are known. Chemical mechanical planarization (CMP) includes holding, rotating and pressing a wafer so that the rotating conductor (eg, Cu metallic) layer 18 is pressed against a wetted planarization/polishing surface under controlled chemical, pressure and temperature conditions. Electrochemical planarization or machining (ECM) is based on electrochemical etching--dissolving a material (eg, a portion of the conductor layer 18) by combining the material with electricity and an aqueous solution of a salt.
FIG. 2 shows a conventional CMP apparatus 30. The apparatus 30 includes a rotatable polishing platen 32 fixed to a rotatable shaft 38, a polishing pad 34 mounted on the platen 32, a rotatable workpiece, carrier 36 arranged proximate to the platen 32 and adapted such that a suitable force (arrow F) is exerted on a workpiece W carried within a recess (not shown) of the carrier 36. The force F is generated, for example, by mechanical, electromechanical and/or pneumatic means well known. The apparatus 30 further includes a polishing slurry supply system including a reservoir or container 40 (eg, temperature controlled), a conduit 42 in fluid communication with the container 40 and the pad 34, and a chemical polishing slurry 44 held within the container 40. The slurry 44 is dispensable onto the pad 34 via the conduit 42.
FIG. 3 shows a conventional electrochemical cell. Metal atoms in an anode A are ionized by electricity from a source of potential B (eg, a battery or other voltage source) and forced into a liquid electrolyte E held by a tank T. The metal anode A dissolves into the solution E at a rate proportional to the electric current, according to Faraday's law. The metal ions from the anode either plate a cathode C, fall out as a precipitate or stay in solution, depending on the chemistry of the metals and the solution.
See, for example, CMP, ECM and other known planarization methods and apparatus discussed in U.S. Pat. Nos: 4,793,895; 4,934,102; 5,225,034; 5,534,106; 5,543,032; 5,567,300; and 5,575,706, which are all incorporated in their entireties by reference. U.S. Pat. No. 5,575,706, CHEMICAL/MECHANICAL PLANARIZATION (CMP) APPARATUS AND POLISH METHOD, Nov. 19, 1996, by Tsai et al discloses controlling a slurry concentration between a wafer and a pad through an application of an electric field between a wafer carrier and a polishing platen.
The present inventors believe that known planarization methods and apparatus have not proven to be entirely satisfactory, because of workpiece throughput limitations resulting from bowing of the workpiece or from damage to the CMOS devices or other components present on the workpiece during planarization.